Power and area efficient MOSFET-C filter for very low frequency applications

New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power biomedical systems. Ranging in value from few hundreds of \hbox{M}\Upomega to few hundreds of \hbox{G}\Upomega , the proposed floating resistors occupy a very small area, and produce accurately tunable characteristics. Using this approach, a low-pass MOSFET-C filter with tunable cutoff frequency (f C =20Hz-184kHz) has been implemented in a conventional 0.18μm CMOS technology. Occupying 0.045mm2/pole, the power consumption of this filter is 540 pW/Hz/pole with a measured IMFDR of 70 d

An area and power optimization technique for CMOS bandgap voltage references

This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in the technology and also the area of bipolar transistors. The proposed technique does not depend on a special process and can be applied for designing bandgap reference circuits with different topologie

A Slew Controlled LVDS Output Driver Circuit in 0.18um CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation in low supply voltages using a conventional 0.18um CMOS technology feasible. The output driver circuit consumes 4.5mA while driving an external 100-Ohm resistor with an output voltage swing of VOD = 400mV, achieving a normalized power dissipation of 3.42mW/Gbps. The area of the LVDS driver circuit is 0.067mm2 and the measured output jitter is sigma_{rms} = 4.5ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5Gbps where the speed will be limited by the load RC time constant

A Widely-Tunable and Ultra-Low-Power MOSFET-C Filter Operating in Subthreshold

A very wide tuning range ultra-low-power MOSFET-C filter is presented. The wide tuning range in this filter has been achieved without using any switchable components or programmable building blocks, and the cutoff frequency of the filter can be adjusted simply through a controlling bias current. The filter has low-pass characteristics with $f_{c}$ = 20Hz to 184kHz while exhibiting a constant power consumption per cutoff frequency over its entire tuning range that is almost four decades wide. The proposed MOSFET-C filter uses PMOS transistors in subthreshold regime for implementing floating and widely adjustable resistors. The ultra high resistivity of the PMOS devices makes them very suitable for implementing very low frequency and compact filters. Realized in 0.18$\mu$m CMOS technology, the filter exhibits a relatively constant noise and linearity performance over its entire tuning range. The active area of the proposed MOSFET-C filter is 0.09mm$^2$

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power-delay performance compared to their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to lower sensitivity to the process and supply voltage variations make STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer scale technologies. An analytical approach for comparing the power-delay performance of these two topologies is proposed

Wide tuning range linearity improved biquadratic transconductor-C filter

This article presents a new technique for improving the linearity performance in biquadratic transconductor-C filters. This improvement has been achieved by applying some modifications to the filter topology which considerably relaxes the linearity requirement on transconductor circuits. Using very simple transconductors, 30 dB improvement in total harmonic distortion compared to the conventional approach has been observed

Ultra-Low Power Mixed-Signal Design Platform Using Subthreshold Source-Coupled Circuits

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed technique is based on using subthreshold source-coupled or current-mode approach for both analog and digital circuits. In addition to possibility of operating with ultra-low power dissipation, because of similar basis for constructing analog and digital parts, a common power management unit could be used for optimizing the power-performance of the entire mixed-signal system. Some circuit examples have been provided to show the performance of the proposed circuits in practice

Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL

Power-frequency scaling in subthreshold source coupled logic (STSCL) systems has been studied and analyzed. It is shown that the operating frequency of such systems can be adjusted over about three decades with linearly proportional power dissipation. The heart of such a system is a phase-locked loop (PLL)-based clock generator (CG) with a very wide tuning range controlling the dynamics of the STSCL system. The design of a wide tuning range PLL utilizing a novel self-adjustable loop filter that generates the reference clock as well as the bias current for the STSCL system is described. The PLL-based CG exhibits linear power-frequency characteristics in order to minimize its power consumption overhead (7 pJ with 350 nA standby current). Implemented in 0.13 μm CMOS, the CG occupies 0.06 mm2 with a supply voltage that can be reduced down to VDD = 0.9 V

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

This article describes some techniques for implementing low- power clock and data recovery (CDR) circuits based on gated- oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient GO CDR are studied and based on that a top-down design methodology is introduced such that the jitter tolerance (JTOL) and frequency tolerance (FTOL) requirements of the system are simultaneously satisfied. A test chip has been implemented in standard digital 0.18 μm CMOS while the proposed CDR circuit consumes only 10.5 mW and occupies 0.045 mm2 silicon area in 2.5 Gbps data bit rate. Measurement results show a good agreement to analyses proofs the capabilities of the proposed approach for implementing low-power GO CDRs